H8SLASH3003 datasheet(342/715 Pages) RENESAS

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Free-running and periodic counter operation

A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A

free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When

the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer

status register (TSR). If the corresponding OVIE bit is set to 1 in the timer interrupt enable

from H'0000. Figure 10-15 illustrates free-running counting.

Figure 10-15 Free-Running Counter Operation

When a channel is set to have its counter cleared by compare match, in that channel TCNT

operates as a periodic counter. Select the output compare function of GRA or GRB, set bit

CCLR1 or CCLR0 in the timer control register (TCR) to have the counter cleared by compare

match, and set the count period in GRA or GRB. After these settings, the counter starts

counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the

count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is

cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU

interrupt is requested at this time. After the compare match, TCNT continues counting up

from H'0000. Figure 10-16 illustrates periodic counting.

TCNT value

H'FFFF

H'0000

STR0 to

STR4 bit

OVF

Time

324

H8/3003 Datasheet(PDF) 342 Page - Renesas Technology Corp