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H8/3003 Datasheet(PDF) 379 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 379 Page - Renesas Technology Corp |
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379 / 715 page  Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output. Figure 10-55 shows the timing. Figure 10-55 Timing of Disabling of ITU Output by External Trigger (Example) Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR. Figure 10-56 shows the timing. Figure 10-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example) ø TIOCA1 pin TOER ITU output I/O port ITU output I/O port Generic input/output Generic input/output ITU output ITU output Input capture signal ITU output pins NN H'C0 H'C0 N: Arbitrary setting (H'C1 to H'FF) ø Address TOCR ITU output pin TOCR address Inverted T 1 T 2 T 3 361 |
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