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H8/3003 Datasheet(PDF) 406 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 406 Page - Renesas Technology Corp |
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406 / 715 page  Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1. Address H'FFA5 Address H'FFA7 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Reserved bits Next data 7 to 4 These bits store the next output data for TPC output group 1 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next data 3 to 0 These bits store the next output data for TPC output group 0 Reserved bits 388 |
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