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H8/3003 Datasheet(PDF) 414 Page - Renesas Technology Corp

Part # H8/3003
Description  microcontroller (MCU)
PDF  715 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3003 Datasheet(HTML) 414 Page - Renesas Technology Corp

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11.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see
section 11.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
G3NOV
0
R/W
0
G0NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP
to TP )
Reserved bits
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP
to TP )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP to TP )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP to TP )
15
12
11
8
74
30
396



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