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H8/3003 Datasheet(PDF) 527 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 527 Page - Renesas Technology Corp |
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527 / 715 page  External Clock • Clock-halving version The external clock signal should have a frequency equal to twice the system clock frequency (ø) and a duty cycle of 40% to 60%. • 1:1 version The external clock frequency should be equal to the system clock frequency (ø). Table 16-3 and figure 16-6 indicate the clock timing. Table 16-3 Clock Timing VCC = 2.7 to 5.5 V VCC = 5.0 V ± 10% Item Symbol Min Max Min Max Unit Test Conditions External clock rise tEXr —10 — 5 ns time External clock fall tEXf —10 — 5 ns time — 30 70 30 70 % ø ≥ 5 MHz 40 60 40 60 % ø < 5 MHz — 40 60 40 60 % Figure 16-6 External Clock Input Timing EXTAL tEXr tEXf a tcyc VCC × 0.5 Ø b tcyc VCC × 0.5 External clock input duty (a/tcyc) ø clock width duty (b/tcyc) Figure 16-6 509 |
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