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H8/3003 Datasheet(PDF) 547 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 547 Page - Renesas Technology Corp |
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547 / 715 page  18.2.2 AC Characteristics Bus timing parameters are listed in table 18-4. Control signal timing parameters are listed in table 18-5. Refresh controller bus timing parameters are listed in table 18-6. Timing parameters of the on-chip supporting modules are listed in table 18-7. Table 18-4 Bus Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz 10 MHz 16 MHz Item Symbol Min Max Min Max Min Max Unit Clock cycle time tCYC 125 500 100 500 62.5 500 ns Clock low pulse width tCL 40 — 30 — 20 — Clock high pulse width tCH 40 — 30 — 20 — Clock rise time tCR —20 — 15 — 10 Clock fall time tCF —20 — 15 — 10 Address delay time tAD —60 — 50 — 30 Address hold time tAH 25 — 20 — 10 — Address strobe delay tASD —60 — 40 — 30 time Write strobe delay time tWSD —60 — 50 — 30 Strobe delay time tSD —60 — 50 — 30 Write data strobe pulse tWSW1* 85 — 60 — 35 — width 1 Write data strobe pulse tWSW2* 150 — 110 — 65 — width 2 Address setup time 1 tAS1 20 — 15 — 10 — Address setup time 2 tAS2 80 — 65 — 40 — Read data setup time tRDS 50 — 35 — 20 — Read data hold time tRDH 0— 0 — 0 — Test Conditions Figure 18-4, Figure 18-5 529 |
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