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H8/3003 Datasheet(PDF) 597 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 597 Page - Renesas Technology Corp |
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597 / 715 page ![]() Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J K L M N RTS RTS Normal*1 21 2 Advanced 2 2 2 SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR SHLR.B Rd 1 SHLR.W Rd 1 SHLR.L ERd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 STC CCR, @ERd 2 1 STC CCR, @(d:16, ERd) 3 1 STC CCR, @(d:24, ERd) 5 1 STC CCR, @–ERd 2 1 2 STC CCR, @aa:16 3 1 STC CCR, @aa:24 4 1 SUB SUB.B Rs, Rd 1 SUB.W #xx:16, Rd 2 SUB.W Rs, Rd 1 SUB.L #xx:32, ERd 3 SUB.L ERs, ERd 1 SUBS SUBS #1/2/4, ERd 1 SUBX SUBX #xx:8, Rd 1 SUBX Rs, Rd 1 TRAPA TRAPA #x:2 Normal*1 21 2 4 Advanced 2 2 2 4 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC XORC #xx:8, CCR 1 Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. For the number of states required for data access, refer to the relevant hardware manual. 3. Not available in the H8/3003. 579 |
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