H8SLASH3003 datasheet(613/715 Pages) RENESAS

613 / 715 page

DTCR0A—Data Transfer Control Register 0A

H'27

DMAC0

(cont)

•

Full address mode

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS0A

R/W

DTS2A

R/W

DTS1A

R/W

Data transfer enable

Data transfer is disabled

Data transfer is enabled

Source address increment/decrement

Data transfer interrupt enable

Data transfer select 0A

Normal mode

Block transfer mode

Data transfer select 2A and 1A

Set both bits to 1

Data transfer size

Byte-size transfer

Word-size transfer

Increment/Decrement Enable

MARA is held fixed

Decremented:

SAID

Bit 5

SAIDE

Bit 4

Incremented:

Interrupt request by DTE bit is disabled

Interrupt request by DTE bit is enabled

If DTSZ = 0, MARA is decremented by 1 after each transfer

If DTSZ = 1, MARA is decremented by 2 after each transfer

If DTSZ = 0, MARA is incremented by 1 after each transfer

If DTSZ = 1, MARA is incremented by 2 after each transfer

595

H8/3003 Datasheet(PDF) 613 Page - Renesas Technology Corp

H8/3003 Datasheet(HTML) 613 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL