H8SLASH3003 datasheet(618/715 Pages) RENESAS

618 / 715 page

DTCR0B—Data Transfer Control Register 0B

H'2F

DMAC0

•

Full address mode

Bit

Initial value

Read/Write

DTME

R/W

—

R/W

DAID

R/W

DAIDE

R/W

TMS

R/W

DTS0B

R/W

DTS2B

R/W

DTS1B

R/W

Data transfer master enable

Data transfer is disabled

Data transfer is enabled

Destination address increment/decrement

Increment/Decrement Enable

MARB is held fixed

Decremented:

DAID

Bit 5

DAIDE

Bit 4

Incremented:

Transfer mode select

Destination is the block area in block transfer mode

Source is the block area in block transfer mode

Data transfer select 2B to 0B

DTS2B

Normal Mode

Auto-request

(burst mode)

Not available

Auto-request

(cycle-steal mode)

Not available

Falling edge of

Bit 2

DTS1B

Bit 1

DTS0B

Bit 0

Low level input at

Data Transfer Activation Source

Block Transfer Mode

Compare match/input capture

A from ITU channel 0

Compare match/input capture

A from ITU channel 1

Compare match/input capture

A from ITU channel 2

Compare match/input capture

A from ITU channel 3

Not available

Falling edge of

Not available

DREQ

If DTSZ = 0, MARB is incremented by 1 after each transfer

If DTSZ = 1, MARB is incremented by 2 after each transfer

If DTSZ = 0, MARB is decremented by 1 after each transfer

If DTSZ = 1, MARB is decremented by 2 after each transfer

600

H8/3003 Datasheet(PDF) 618 Page - Renesas Technology Corp

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