H8SLASH3003 datasheet(636/715 Pages) RENESAS

636 / 715 page

TCR0—Timer Control Register 0

H'64

ITU0

Bit

Initial value

Read/Write

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Timer prescaler 2 to 0

Clock edge 1 and 0

Counter clear 1 and 0

TCNT is not cleared

TCNT is cleared by GRB compare match or input capture

Synchronous clear:

Bit 6

Bit 5

TCNT Clear Source

CCLR1 CCLR0

TCNT is cleared by GRA compare match or input capture

Rising edges counted

Both edges counted

Bit 4

Bit 3

—

Counted Edges of External Clock

CKEG1 CKEG0

Falling edges counted

TPSC2

TCNT Clock Source

Internal clock: ø

Internal clock: ø/2

Internal clock: ø/4

Internal clock: ø/8

External clock A: TCLKA input

External clock B: TCLKB input

External clock C: TCLKC input

Bit 2

TPSC1

Bit 1

TPSC0

Bit 0

External clock D: TCLKD input

TCNT is cleared in synchronization

with other synchronized timers

618

H8/3003 Datasheet(PDF) 636 Page - Renesas Technology Corp

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