H8SLASH3003 datasheet(145/715 Pages) RENESAS

145 / 715 page

6.3.6 Interconnections with Memory (Example)

For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus

width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the

connection of both high-speed and low-speed devices.

Figure 6-18 shows an example of interconnections between the H8/3003 and memory. Figure 6-17

shows a memory map for this example.

A 256-kword

× 16-bit EPROM is connected to area 0. This device is accessed in three states via a

16-bit bus.

Two 32-kword

× 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These

devices are accessed in two states via a 16-bit bus.

One 32-kword

× 8-bit SRAM (SRAM3) is connected to area 7. This device is accessed via an

8-bit bus, using three-state access with an additional wait state inserted in pin auto-wait mode.

Figure 6-17 Memory Map (Example)

H'000000

H'03FFFF

H'1FFFFF

H'200000

H'20FFFF

H'210000

H'3FFFFF

H'E00000

H'E07FFF

H'FFFFFF

Not used

On-chip RAM

On-chip registers

EPROM

Not used

SRAM 1, 2

Not used

SRAM 3

Area 0

16-bit, three-state-access area

Area 1

16-bit, two-state-access area

Area 7

8-bit, three-state-access area

(one auto-wait state)

127

H8/3003 Datasheet(PDF) 145 Page - Renesas Technology Corp

H8/3003 Datasheet(HTML) 145 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL