H8SLASH3003 datasheet(164/715 Pages) RENESAS

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Table 7-4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles

Area 3 Settings

Read/Write Cycle by CPU or DMAC

Refresh Cycle

2-state-access area

• 3 states

(AST3 = 0)

• Wait states cannot be inserted

3-state-access area

• 3 states

(AST3 = 1)

• Wait states can be inserted

To insert refresh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7-3 shows the state

transitions for execution of refresh cycles.

When the first refresh request occurs after exit from the reset state or standby mode, the refresh

controller does not execute a refresh cycle, but goes into the refresh request pending state. Note

this point when using a DRAM that requires a refresh cycle for initialization.

When a refresh request occurs in the refresh request pending state, the refresh controller acquires

the bus right, then executes a refresh cycle. If another refresh request occurs during execution of

the refresh cycle, it is ignored.

Figure 7-3 State Transitions for Refresh Cycle Execution

Refresh

request*

Refresh

request*

Exit from reset or standby mode

Refresh request pending state

Requesting bus right

Executing refresh cycle

Refresh request

Bus granted

End of refresh

cycle

Note:

A refresh request is ignored if it occurs while the refresh controller is requesting the

bus right or executing a refresh cycle.

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H8/3003 Datasheet(PDF) 164 Page - Renesas Technology Corp