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H8/3003 Datasheet(PDF) 192 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 192 Page - Renesas Technology Corp |
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192 / 715 page  8.1.2 Block Diagram Figure 8-1 shows a DMAC block diagram. The DMAC is divided into two groups (group 0 and group 1) of four channels each. Figure 8-1 Block Diagram of DMA Controller (Group 0: Four Channels) IMIA0 IMIA1 IMIA2 IMIA3 TXI0 RXI0 DREQ0 DREQ1 TEND0 TEND1 DEND0A DEND0B DEND1A DEND1B DTCR0A DTCR0B DTCR1A DTCR1B Control logic Data buffer Address buffer Arithmetic-logic unit MAR0A MAR0B MAR1A MAR1B IOAR0A IOAR0B IOAR1A IOAR1B ETCR0A ETCR0B ETCR1A ETCR1B Internal address bus Internal interrupts Interrupt signals Internal data bus Legend DTCR: MAR: IOAR: ETCR: Data transfer control register Memory address register I/O address register Execute transfer count register Channel 0A Channel 0B Channel 1A Channel 1B Channel 0 Channel 1 174 |
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