H8SLASH3003 datasheet(201/715 Pages) RENESAS

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8.2.4 Data Transfer Control Registers (DTCR)

A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the

operation of one DMAC channel.

The DTCRs are initialized to H'00 by a reset and in standby mode.

Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the

DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when

activated as specified by bits DTS2 to DTS0 . When DTE is 0, the channel is disabled and does

not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.

Bit 7

DTE

Description

Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0

(Initial value)

when the specified number of transfers have been completed.

Data transfer is enabled

If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS0

R/W

DTS2

R/W

DTS1

R/W

Data transfer enable

Enables or disables

data transfer

Data transfer interrupt enable

Enables or disables the CPU interrupt

at the end of the transfer

Data transfer select

These bits select the data

transfer activation source

Data transfer size

Selects byte or

word size

Data transfer

increment/decrement

Selects whether to

increment or decrement

the memory address

Repeat enable

Selects repeat

mode

183

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