H8SLASH3003 datasheet(224/715 Pages) RENESAS

224 / 715 page

8.4.5 Normal Mode

In normal mode the A and B channels are combined. One byte or word is transferred per request.

A designated number of these transfers are executed. Addresses are specified in MARA and

MARB. Table 8-9 indicates the register functions in I/O mode.

Table 8-9 Register Functions in Normal Mode

Function

Initial Setting

Operation

Source address

Incremented or

decremented once per

transfer, or held fixed

Destination

Incremented or

address register

address

decremented once per

transfer, or held fixed

Transfer counter

Number of

Decremented once per

transfers

transfer

Legend

MARA:

Memory address register A

MARB:

Memory address register B

ETCRA: Execute transfer count register A

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred.

The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by

1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer

ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count

is 65,536, obtained by setting ETCRA to H'0000.

Figure 8-8 illustrates how normal mode operates.

MARA

ETCRA

MARB

206

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