H8SLASH3003 datasheet(248/715 Pages) RENESAS

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8.5 Interrupts

The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority.

Table 8-13 DMAC Interrupts

Description

Group

Interrupt

Short Address Mode

Full Address Mode

Interrupt Priority

DEND0A

End of transfer on channel 0A

End of transfer on

High

channel 0

DEND0B

End of transfer on channel 0B

—

DEND1A

End of transfer on channel 1A

End of transfer on

channel 1

DEND1B

End of transfer on channel 1B

—

DEND2A

End of transfer on channel 2A

End of transfer on

channel 2

DEND2B

End of transfer on channel 2B

—

DEND3A

End of transfer on channel 3A

End of transfer on

channel 3

DEND3B

End of transfer on channel 3B

—

Low

Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control

The interrupt priority order among channels is channel 0 > channel 1 > channel 2 > channel 3, and

channel A > channel B. The interrupt priority order between groups can be modified in interrupt

priority register B (IPRB).

Figure 8-26 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and

DTIE = 1.

230

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