H8SLASH3003 datasheet(286/715 Pages) RENESAS

286 / 715 page

9.9 Port B

9.9.1 Overview

Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the

programmable timing pattern controller (TPC), input/output (TIOCB4, TIOCB3, TIOCA4,

TIOCA3) and output (TOCXB4, TOCXA4) by the 16-bit integrated timer-pulse unit (ITU), input

(DREQ1, DREQ0) to the DMA controller (DMAC), and ADTRG input to the A/D converter. Port

B has the same set of pin functions in all operating modes. Figure 9-12 shows the pin

configuration of port B.

Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs.

Figure 9-12 Port B Pin Configuration

9.9.2 Register Descriptions

Table 9-15 summarizes the registers of port B.

Table 9-15 Port B Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'FFD4

Port B data direction register

PBDDR

H'00

H'FFD6

Port B data register

PBDR

R/W

H'00

Note: * Lower 16 bits of the address.

Port B

PB (input/output)/TP

(output)/DREQ (input)/

(input)

PB (input/output)/TP

(output)/DREQ (input)

PB (input/output)/TP

(output)/TOCXB (output)

PB (input/output)/TP

(output)/TOCXA (output)

Port B pins

PB (input/output)/TP

(output)/TIOCB (input/output)

PB (input/output)/TP

(output)/TIOCA (input/output)

PB (input/output)/TP

(output)/TIOCB (input/output)

PB (input/output)/TP

(output)/TIOCA (input/output)

ADTRG

268

H8/3003 Datasheet(PDF) 286 Page - Renesas Technology Corp

H8/3003 Datasheet(HTML) 286 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL