H8SLASH3003 datasheet(326/715 Pages) RENESAS

326 / 715 page

The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by

either word or byte access.

Buffer registers are initialized to H'FFFF by a reset and in standby mode.

10.2.10 Timer Control Registers (TCR)

TCR is an 8-bit register. The ITU has five TCRs, one in each channel.

Channel

Abbreviation

Function

TCR0

TCR1

TCR2

TCR3

TCR4

Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects

the edge or edges of external clock sources, and selects how the counter is cleared.

TCR is initialized to H'80 by a reset and in standby mode.

Bit 7—Reserved: Read-only bit, always read as 1.

TCR controls the timer counter. The TCRs in all channels are

functionally identical. When phase counting mode is selected in

channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to

TPSC0 in TCR2 are ignored.

Bit

Initial value

Read/Write

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Timer prescaler 2 to 0

These bits select the

counter clock

Reserved bit

Clock edge 1/0

These bits select external clock edges

Counter clear 1/0

These bits select the counter clear source

308

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