H8SLASH3002 datasheet(156/700 Pages) RENESAS

156 / 700 page

7.1.3 Input/Output Pins

Table 7-1 summarizes the refresh controller’s input/output pins.

Table 7-1 Refresh Controller Pins

Signal

Name

Abbr.

I/O

Function

RFSH

Refresh

RFSH

Output

Goes low during refresh cycles; used

to refresh DRAM and PSRAM

HWR

Upper write/upper column

UW/UCAS Output

Connects to the

UW pin of 2WE

address strobe

DRAM or

UCAS pin of 2CAS DRAM

LWR

Lower write/lower column

LW/LCAS

Output

Connects to the

LW pin of 2WE DRAM

address strobe

LCAS pin of 2CAS DRAM

Column address strobe/

CAS/WE

Output

Connects to the

CAS pin of 2WE

write enable

DRAM or

WE pin of 2CAS DRAM

CS3

Row address strobe

RAS

Output

Connects to the

RAS pin of DRAM

7.1.4 Register Configuration

Table 7-2 summarizes the refresh controller’s registers.

Table 7-2 Refresh Controller Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'FFAC

Refresh control register

RFSHCR

R/W

H'02

H'FFAD

Refresh timer control/status register

RTMCSR

R/W

H'07

H'FFAE

Refresh timer counter

RTCNT

R/W

H'00

H'FFAF

Refresh time constant register

RTCOR

R/W

H'FF

Note: * Lower 16 bits of the address.

141

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