M38K09RFS datasheet(214/328 Pages) RENESAS

214 / 328 page

2.10 Frequency synthesizer (PLL)

Rev.2.00

Oct 05, 2006

page 85 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

2.10.3 Functional description

The frequency synthesizer generates the 48 MHz clock which is multiples of the external input reference

f(XIN) and is needed for operating USB function. When using the USB function, set PLL enable bit of PLL

control register (PLLCON: address 0FF816) to “1” (enabled) to send the 48 MHz PLL output clock (fVCO) into

USB function control unit. Figure 2.10.5 shows the block diagram for the frequency synthesizer circuit.

Table 2.10.1 PLL operation mode selection bits setting example

f(XIN)

6 MHZ

12 MHZ

PLL operation mode

selection bits *

48 MHZ

fVCO

q fVCO (PLL output clock)

fVCO is generated by multiplying PLL input clock according to the contents of PLL operation mode

selection bits (bits 6, 5 of PLLCON), where

fVCO =f(XIN) ✕ n, n:value selected by PLL operation mode selection bits

Set PLL operation mode selection bits so that fVCO may be set to 48 MHz.

While the PLL enable bit is “0” (disabled), fVCO retains “L” level (except when PLL operation mode

selection bits are set to “002”).

Table 2.10.1 shows the example of PLL operation mode selection bits setting.

PLL

fUSB

f(XIN)

fVCO

PLLCON

Division circuit

fSYN

(address 0FF816)

USBCON

(address 001016)

Fig. 2.10.5 Block diagram for frequency synthesizer circuit

*: PLL control register (bits 6,5)

q fUSB (USB clock)

Either f(XIN) (main clock) or fVCO (PLL output clock) can be selected for fUSB by USB clock select bit

of USB control register (bit6 of USBCON: address 001016), and it is supplied to the USB function

control circuit. When supplying fVCO to the USB function control circuit, after setting PLL enable bit

to “1” (enabled) and then set USB clock select bit to “1” (USB clock).

Furthermore, when PLL operation mode selection bits are set to “002”, the clock input into PLL is

used as fVCO, which is not multiplied, regardless of PLL operation enabled or disabled.

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