M38K09RFS datasheet(212/328 Pages) RENESAS

212 / 328 page

2.10 Frequency synthesizer (PLL)

Rev.2.00

Oct 05, 2006

page 83 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

2.10 Frequency synthesizer (PLL)

This paragraph explains the registers setting method and the notes related to the frequency synthesizer

(PLL circuit).

2.10.1 Memory map

Fig. 2.10.2 Structure of USB control register

2.10.2 Related registers

CPU mode register (CPUM)

USB control register (USBCON)

003B16

001016

0FF816

PLL control register (PLLCON)

Fig. 2.10.1 Memory map of registers related to PLL

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

USB control register

Remote wakeup bit

TrON output control bit

TrON output enable bit

USB reference voltage

control bit

USB reference voltage

enable bit

USB difference input

enable bit

USB clock select bit

USB module operation

enable bit

0 : “L” output mode (valid in TRONE = “1”)

1 : “H” output mode (valid in TRONE = “1”)

0 : TrON port output disabled (Hi-Z state)

1 : TrON port output enabled

0 : Normal mode (valid in VREFE = “1”)

1 : Low current mode (valid in VREFE = “1”)

0 : USB reference voltage circuit operation disabled

1 : USB reference voltage circuit operation enabled

0 : Upstream-port difference input circuit operation disabled

1 : Upstream--port difference input circuit operation enabled

0 : External oscillating clock f(XIN)

1 : PLL circuit output clock fVCO

0 : USB module reset

1 : USB module operation enabled

0 : Returning to BUS idle state by writing “1” first

and then “0”. (Remote wakeup signal)

1 : K-state output

USB control register (USBCON)

[Address 1016]

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