M38K09RFS datasheet(288/328 Pages) RENESAS

288 / 328 page

3.4 List of registers

Rev.2.00

Oct 05, 2006

page 47 of 89

38K0 Group

REJ09B0337-0200

APPENDIX

Fig. 3.4.21 Structure of EP02 control register 2

Fig. 3.4.22 Structure of EP03 control register 2

B0VAL02

b7:b1

–

EP02 control register 2 (EP02CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

Buffer 0 enable bit

Not used

When the selected endpoint is IN, writing “1” to this bit

makes the transmitting data a set state (SIE is possible

to read).

When the selected endpoint is OUT, writing “1” to this

bit makes data reception possible (SIE is possible to

write).

Write “0” when writing.

“0” is read when reading.

B0VAL03

b7:b1

–

EP03 control register 2 (EP03CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

Buffer 0 enable bit

Not used

When the selected endpoint is IN, writing “1” to this bit

makes the transmitting data a set state (SIE is possible

to read).

When the selected endpoint is OUT, writing “1” to this

bit makes data reception possible (SIE is possible to

write).

Write “0” when writing.

“0” is read when reading.

Fig. 3.4.23 Structure of EP00 control register 3

Control transfer completion

enable bit

Not used

CTENDE00

b7:b1

–

EP00 control register 3 (EP00CON3) [address 001C16]

0 : NAK transmission in the status stage

1 : Control transfer completion enabled (SIE transmits

NULL/ACK.) (valid in PID00 = “012”)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Bit name

Bit symbol

At reset

Function

H/W

S/W

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