M38K09RFS datasheet(287/328 Pages) RENESAS

287 / 328 page

3.4 List of registers

Rev.2.00

Oct 05, 2006

page 46 of 89

38K0 Group

REJ09B0337-0200

APPENDIX

Fig. 3.4.20 Structure of EP01 control register 2

B0VAL01

b7:b1

–

EP01 control register 2 (EP01CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

Buffer 0 enable bit

Not used

When the selected endpoint is IN, writing “1” to this bit

makes the transmitting data a set state (SIE is possible

to read).

When the selected endpoint is OUT, writing “1” to this

bit makes data reception possible (SIE is possible to

write).

Write “0” when writing.

“0” is read when reading.

Fig. 3.4.18 Structure of EP03 control register 1

Fig. 3.4.19 Structure of EP00 control register 2

Response PID bit

Not used

PID03

[1:0]

b7:b2

–

EP03 control register 1 (EP03CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of over-max. packet size :

B1 is set to “1” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Buffer enable bit

Not used

BVAL00

b7:b1

–

EP00 control register 2 (EP00CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

0 : NAK transmission (SIE is disabled to read a buffer.)

1 : Transmitting/receiving data set state (SIE is possible

to read from/write to a buffer.)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

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