M38K09RFS datasheet(283/328 Pages) RENESAS

283 / 328 page

3.4 List of registers

Rev.2.00

Oct 05, 2006

page 42 of 89

38K0 Group

REJ09B0337-0200

APPENDIX

Fig. 3.4.9 Structure of USB interrupt source register

USB function/Endpoint 0

interrupt bit

USB function/Endpoint 1

interrupt bit

USB function/Endpoint 2

interrupt bit

USB function/Endpoint 3

interrupt bit

Not used

Suspend interrupt bit

Resume interrupt bit

EP00

EP01

EP02

EP03

b5:b4

SUS

RSM

–

USB interrupt source register (USBIREQ) [address 001716]

Bit name

Bit symbol

At reset

Function

H/W

S/W

This bit is set to “1” when any one of EP00 interrupt

source register’s bits at least is set to “1”.

This bit is cleared to “0” by clearing EP00 interrupt

source register to “0016”.

Writing to this bit causes no state change.

This bit is set to “1” when any one of EP01 interrupt

source register’s bits at least is set to “1”.

This bit is cleared to “0” by clearing EP01 interrupt

source register to “0016”.

Writing to this bit causes no state change.

This bit is set to “1” when any one of EP02 interrupt

source register’s bits at least is set to “1”.

This bit is cleared to “0” by clearing EP02 interrupt

source register to “0016”.

Writing to this bit causes no state change.

This bit is set to “1” when any one of EP03 interrupt

source register’s bits at least is set to “1”.

This bit is cleared to “0” by clearing EP03 interrupt

source register to “0016”.

Writing to this bit causes no state change.

Write “0” when writing.

“0” is read when reading.

0 : No interrupt request issued

1 : Interrupt request issued

This bit is set to “1” when detecting 3 ms or more of J-

state, using USB clock (fUSB) at 48 MHz.

“0” can be set by software, but “1” cannot be set.

This bit is set to “1” when the USB bus state changes

from J-state to K-state or SE0 in the resume interrupt

enable bit = “1”. It is also “1” in the condition of internal

clock stopped.

This bit is cleared to “0” by clearing the resume

interrupt enable bit.

Writing to this bit causes no state change.

–: State remaining

Fig. 3.4.10 Structure of Endpoint index register

Endpoint index bit

Not used

EPIDX [1:0]

b7:b3

–

Endpoint index register (USBINDEX) [address 001816]

b1 b0

0 0 : Endpoint 0

0 1 : Endpoint 1

1 0 : Endpoint 2

1 1 : Endpoint 3

Write “0” when writing.

“0” is read when reading.

Bit name

Bit symbol

At reset

Function

–: State remaining

H/W

S/W

0 0

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