M38K09RFS datasheet(286/328 Pages) RENESAS

286 / 328 page

3.4 List of registers

Rev.2.00

Oct 05, 2006

page 45 of 89

38K0 Group

REJ09B0337-0200

APPENDIX

Fig. 3.4.15 Structure of EP00 control register 1

Response PID bit

Not used

PID00 [1:0]

b7:b2

–

EP00 control register 1 (EP00CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of control transfer error:

B1 is set to “1” by the hardware.

At reception of SETUP token:

B1 and b0 are cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Fig. 3.4.16 Structure of EP01 control register 1

Response PID bit

Not used

PID01

[1:0]

b7:b2

–

EP01 control register 1 (EP01CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of over-max. packet size :

B1 is set to “1” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Response PID bit

Not used

PID02

[1: 0]

b7:b2

–

EP02 control register 1 (EP02CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of over-max. packet size :

B1 is set to “1” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Fig. 3.4.17 Structure of EP02 control register 1

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