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AT89LP6440 Datasheet(PDF) 71 Page - ATMEL Corporation |
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AT89LP6440 Datasheet(HTML) 71 Page - ATMEL Corporation |
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71 / 194 page ![]() 71 3706A–MICRO–9/09 AT89LP6440 - Preliminary 13.2 Input Capture Mode The Compare/Capture Array provides a variety of capture modes suitable for time-stamping events or performing measurements of pulse width, frequency, slope, etc. CCA channels are configured for capture mode by clearing the CCMx bit in the associated CCCx register to 0. Each time a capture event occurs, the contents of Timer 2 (TH2 and TL2) are transferred to the 16-bit data register of the corresponding channel, and the channel’s interrupt flag CCFx is set in T2CCF. Optionally, the capture event may also clear Timer 2 to 0000H by setting the CTCx bit in CCCx. The capture event is defined by the CxM 2-0 bits in CCCx and may be either externally or internally generated. A diagram of a CCA channel in capture mode is shown in Figure 13-2. Figure 13-2. CCA Capture Mode Diagram Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected Table 13-4. T2CCF – Timer/Counter 2 Compare/Capture Flags T2CCF Address = 0D5H Reset Value = XXXX 0000B Not Bit Addressable – – – – CCFD CCFC CCFB CCFA Bit 7 654 321 0 Symbol Function CCFD Channel D Compare/Capture Interrupt Flag. Set by a compare/capture event on channel D. Must be cleared by software. CCFD will generate an interrupt when CIEND = 1 and ECC = 1. CCFC Channel C Compare/Capture Interrupt Flag. Set by a compare/capture event on channel C. Must be cleared by software. CCFC will generate an interrupt when CIENC = 1 and ECC = 1. CCFB Channel B Compare/Capture Interrupt Flag. Set by a compare/capture event on channel B. Must be cleared by software. CCFB will generate an interrupt when CIENB = 1 and ECC = 1. CCFA Channel A Compare/Capture Interrupt Flag. Set by a compare/capture event on channel A. Must be cleared by software. CCFA will generate an interrupt when CIENA = 1 and ECC = 1. TL2 TH2 CCxL CCxH CCCx Interrupt (P2.x) CCx T2CCC T2CCL T2CCH 0 1 2 3 4 5 6 7 “0” Timer 0 Overflow Timer 1 Overflow Comparator A Comparator B 00H 00H CTCx CCFx CIENx CxM2-0 |
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