AT89LP6440 datasheet(55/194 Pages) ATMEL

55 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

11.5

Pulse Width Modulation

On the AT89LP6440, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetri-

cal (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in

TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin,

T0 or T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0 (P3.4) and T1

(P3.5) must be configured in an output mode. The Timer Overflow Flags and Interrupts will con-

tinue to function while in PWM Mode and Timer 1 may still generate the baud rate for the UART.

The timer GATE function also works in PWM mode, allowing the output to be halted by an exter-

nal input. Each PWM channel has four modes selected by the mode bits in TMOD.

An example waveform for Timer 0 in PWM Mode 0 is shown in Figure 11-5. TH0 acts as an 8-bit

counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is

set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low.

Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to

RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM

output low.

Figure 11-5. 8-bit Asymmetrical Pulse Width Modulation

Table 11-4.

TCONB

– Timer/Counter Control Register B

TCONB = 91H

Reset Value = 0010 0100B

Not Bit Addressable

PWM1EN

PWM0EN

PSC12

PSC11

PSC10

PSC02

PSC01

PSC00

Bit

543

Symbol

Function

PWM1EN

Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5).

PWM0EN

Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4).

PSC12

PSC11

PSC10

Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1. After reset PSC1 = 100B which

enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89S2051.

PSC02

PSC01

PSC00

Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1. After reset PSC0 = 100B which

enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C52.

FFH

00H

RH0

(P3.4)T0

TF0 Set

TH0

time

AT89LP6440 Datasheet(PDF) 55 Page - ATMEL Corporation

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