AT89LP6440 datasheet(39/194 Pages) ATMEL

39 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

The IPxD bits located at the seventh bit of IP, IPH, IP2 and IP2H can be used to disable all inter-

rupts of a given priority level, allowing software implementations of more complex interrupt

priority handling schemes such as level-based round-robin scheduling.

The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,

depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-

rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears

the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-

rupt was level activated, then the external requesting source (rather than the on-chip hardware)

controls the request flag.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in

their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is

generated, the on-chip hardware clears the flag that generated it when the service routine is

vectored to. The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register

T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service rou-

tine. The service routine normally must determine whether TF2 or EXF2 generated the interrupt

and that bit must be cleared by software.

The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON. Neither of these

flags is cleared by hardware when the CPU vectors to the service routine. The service routine

normally must determine whether RI or TI generated the interrupt and that bit must be cleared by

software.

The Serial Peripheral Interface Interrupt is generated by the logic OR of SPIF, MODF and TXE

in SPSR. None of these flags is cleared by hardware when the CPU vectors to the service rou-

tine. The service routine normally must determine which bit generated the interrupt and that bit

must be cleared by software.

A logic OR of all eight flags in the GPIF register causes the General-purpose Interrupt. None of

these flags is cleared by hardware when the service routine is vectored to. The service routine

must determine which bit generated the interrupt and that bit must be cleared in software. If the

interrupt was level activated, then the external requesting source must de-assert the interrupt

before the flag may be cleared by software.

The CFA and CFB bits in ACSRA and ACSRB respectively generate the Comparator Interrupt.

The service routine must normally determine whether CFA or CFB generated the interrupt, and

the bit must be cleared by software. The DAC/ADC Conversion Interrupt is generated by ADIF in

DADC. On-chip hardware clears the ADIF flag when vectoring to the service routine.

A logic OR of the four least significant bits in the T2CCF register causes the Compare/Capture

Array Interrupt. None of these flags is cleared by hardware when the service routine is vectored

to. The service routine must determine which bit generated the interrupt and that bit must be

cleared in software.

The Two-Wire Interface Interrupt is generated by TWIF in TWCR. The flag is not cleared by

hardware when the CPU vectors to the service routine. The service routine normally must deter-

mine the status in TWSR and respond accordingly before the bit is cleared by software.

All of the bits that generate interrupts can be set or cleared by software, with the same result as

though they had been set or cleared by hardware. That is, interrupts can be generated and

pending interrupts can be canceled in software.

AT89LP6440 Datasheet(PDF) 39 Page - ATMEL Corporation

AT89LP6440 Datasheet(HTML) 39 Page - ATMEL Corporation

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