AT89LP6440 datasheet(13/194 Pages) ATMEL

13 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Some internal data memory spaces are mapped into portions of the XDATA address space. In

this case the lower address ranges will access internal resources instead of external memory.

Addresses above the range implemented internally will default to XDATA. The AT89LP6440

supports up to 52K or 60K bytes of external memory when using the internally mapped memo-

ries. Setting the EXRAM bit (AUXR.1) to one will force all MOVX instructions to access the entire

64KB XDATA regardless of their address (See “AUXR – Auxiliary Control Register” on page 17).

3.3.2

EDATA

The Extra RAM is a portion of the external memory space implemented as an internal 4K byte

auxiliary RAM. The Extra RAM is mapped into the EDATA space at the bottom of the external

memory address space, from 0000H to 0FFFH. MOVX instructions to this address range will

access the internal Extra RAM. EDATA can be accessed with both 16-bit (MOVX @DPTR) and

8-bit (MOVX @Ri) addresses. When 8-bit addresses are used, the PAGE register (086H) sup-

plies the upper address bits. The PAGE register breaks EDATA into sixteen 256-byte pages. A

page cannot be specified independently for MOVX @R0 and MOVX @R1. Setting PAGE above

0FH enables XDATA access, but does not change the value of Port 2. When 16-bit addresses

are used (DPTR), the IAP bit (MEMCON.7) must be zero to access EDATA. MOVX instructions

to EDATA require a minimum of 2 clock cycles.

3.3.3

FDATA

The Flash Data Memory is a portion of the external memory space implemented as an internal

nonvolatile data memory. Flash Data Memory is enabled by setting the DMEN bit (MEMCON.3)

to one. When IAP = 0 and DMEN = 1, the Flash Data Memory is mapped into the FDATA space,

directly above the EDATA space near the bottom of the external memory address space, from

1000H to 2FFFH. (See Figure 3-3). MOVX instructions to this address range will access the

internal nonvolatile memory. FDATA is not accessible while DMEN = 0. FDATA can be

accessed only by 16-bit (MOVX @DPTR) addresses. MOVX @Ri instructions to the FDATA

address range will access external memory. Addresses above the FDATA range are mapped to

XDATA. MOVX instructions to FDATA require a minimum of 4 clock cycles.

3.3.3.1

Write Protocol

The FDATA address space accesses an internal nonvolatile data memory. This address space

can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a

more complex protocol and take several milliseconds to complete. The AT89LP6440 uses an

idle-while-write architecture where the CPU is placed in an idle state while the write occurs.

When the write completes, the CPU will continue executing with the instruction after the

MOVX @DPTR,A instruction that started the write. All peripherals will continue to function during

the write cycle; however, interrupts will not be serviced until the write completes.

Table 3-2.

PAGE

– EDATA Page Register

PAGE = 86H

Reset Value = 0000 0000B

Not Bit Addressable

PAGE.7

PAGE.6

PAGE.5

PAGE.4

PAGE.3

PAGE.2

PAGE.1

PAGE.0

Bit

543

Symbol

Function

PAGE7-0

Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions when PAGE < 10H. Any PAGE

value between 10H and FFH will selected XDATA; however, this value will not be output on P2.

AT89LP6440 Datasheet(PDF) 13 Page - ATMEL Corporation

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