AT89LP6440 datasheet(88/194 Pages) ATMEL

88 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

16.3

More About Mode 0

In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. Serial

data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmit-

ted/received, with the LSB first. Figure 16-1 on page 89 shows a simplified functional diagram of

the serial port in Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the

oscillator frequency by setting/clearing the SMOD1 bit. However, changing SMOD1 has an

effect on the relationship between the clock and data as described below. The baud rate can

also be generated by Timer 1 by setting TB8. Table 16-4 lists the baud rate options for Mode 0.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write

to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX

Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse

between “write to SBUF” and activation of SEND.

SEND transfers the output of the shift register to the alternate output function line of P3.0, and

also transfers Shift Clock to the alternate output function line of P3.1. As data bits shift out to the

right, “0”s come in from the left. When the MSB of the data byte is at the output position of the

shift register, the “1” that was initially loaded into the 9th position is just to the left of the MSB,

and all positions to the left of that contain “0”s. This condition flags the TX Control block to do

one last shift, then deactivate SEND and set TI.

Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-

trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next

clock phase. RECEIVE enables Shift Clock to the alternate output function line of P3.1. As data

bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the

right-most position arrives at the left-most position in the shift register, it flags the RX Control

block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.

The relationship between the shift clock and data is determined by the combination of the SM2

and SMOD1 bits as listed in Table 16-5 and shown in Figure 16-2. The SM2 bit determines the

idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the

output data is stable for both edges of the clock, or just one.

Table 16-4.

Mode 0 Baud Rates

TB8

SMOD1

Baud Rate

fSYS/4

fSYS/2

(Timer 1 Overflow) / 4

(Timer 1 Overflow) / 2

Table 16-5.

Mode 0 Clock and Data Modes

SM2

SMOD1

Clock Idle

Data Changed

Data Sampled

High

While clock is high

Positive edge of clock

High

Negative edge of clock

Positive edge of clock

Low

While clock is low

Negative edge of clock

Low

Negative edge of clock

Positive edge of clock

AT89LP6440 Datasheet(PDF) 88 Page - ATMEL Corporation

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