AT89LP6440 datasheet(25/194 Pages) ATMEL

25 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

•In some cases, both data pointers must be used simultaneously. To prevent frequent toggling

of DPS, the AT89LP6440 supports a prefix notation for selecting the opposite data pointer

per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed

with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer.

Some assemblers may support this operation by using the /DPTR operand. For example, the

following code performs a block copy within EDATA:

MOV

DPCF, #00H

; DPS = 0

MOV

DPTR, #SRC

; load source address to dptr0

MOV

/DPTR, #DST

; load destination address to dptr1

MOV

R7, #BLKSIZE

; number of bytes to copy

COPY:

MOVX A, @DPTR

; read source (dptr0)

INC

DPTR

; next src (dptr0+1)

MOVX @/DPTR, A

; write destination (dptr1)

INC

/DPTR

; next dst (dptr1+1)

DJNZ R7, COPY

For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:

EX:

0A5H

INC

DPTR

; equivalent to INC /DPTR

Table 5-1.

DSPR

– Digital Signal Processing Configuration Register

DSPR = E2H

Reset Value = 0000 0000B

Not Bit Addressable

MRW1

MRW0

SMLB

SMLA

CBE1

CBE0

MVCD

DPRB

Bit

543

Symbol

Function

MRW1-0

M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH (E5H) and

MACL (E4H) as shown in Figure 5-5. For example, MRW = 10B for normal 16-bit fixed-point operations where the lowest

order portion of the fractional result is discarded.

SMLB

Signed Multiply Operand B. When SMLB = 0, the MUL AB instruction treats the contents of B as an unsigned value.

When SMLB = 1, the MUL AB instruction interprets the contents of B as a signed two’s complement value. SMLB does

not affect the MAC operation.

SMLA

Signed Multiply Operand A. When SMLA = 0, the MUL AB instruction treats the contents of ACC as an unsigned value.

When SMLA = 1, the MUL AB instruction interprets the contents of ACC as a signed two’s complement value. SMLA

does not affect the MAC operation.

CBE1

DPTR1 Circular Buffer Enable. Set CBE1 = 1 to configure DPTR1 for circular addressing over the two circular buffer

address ranges. Clear CBE1 for normal DPTR operation.

CBE0

DPTR0 Circular Buffer Enable. Set CBE0 = 1 to configure DPTR0 for circular addressing over the two circular buffer

address ranges. Clear CBE0 for normal DPTR operation.

MVCD

MOVC Index Disable. When MVCD = 0, the MOVC A, @A+DPTR instruction functions normally with indexed

addressing. Setting MVCD = 1 disables the indexed addressing mode such that MOVC A, @A+DPTR functions as

MOVC A, @DPTR.

DPRB

DPTR1 Redirect to B. DPRB selects the source/destination register for MOVC/MOVX instructions that reference DPTR1.

When DPRB = 0, ACC is the source/destination. When DPRB = 1, B is the source/destination. DPRB does not change

the index register for MOVC instructions.

AT89LP6440 Datasheet(PDF) 25 Page - ATMEL Corporation

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