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MMA8450QT Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

Part # MMA8450QT
Description  3-Axis, 8-bit/12-bit Digital Accelerometer
PDF  57 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMA8450QT Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc

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35
Freescale Semiconductor
MMA8450Q
0x2D: TRANSIENT_THS Transient Threshold Register
The TRANSIENT_THS register sets the threshold limit for the high pass filtered acceleration. The value in the
TRANSIENT_THS register corresponds to a g value which is compared against the values of OUT_X_DELTA, OUT_Y_DELTA,
and OUT_Z_DELTA. If the acceleration exceeds the threshold limit an event flag is raised and an interrupt is generated if
interrupts are enabled.
The minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range
of 0 to 127.
Therefore:
•
If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum
is 8g.
•
If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The
maximum is 4g.
•
If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The
maximum is 2g.
•
The DBCNTM bit behaves in the same manner described previously for the Motion/Freefall 1.
0x2E: TRANSIENT_COUNT Transient Debounce Register
The TRANSIENT_COUNT sets the minimum number of debounce counts continuously matching the condition where the
unsigned value of OUT_X_DELTA or OUT_Y_DELTA or OUT_Z_DELTA register is greater than the user specified value of
TRANSIENT_THS.
The time step for the Transient detection debounce counter is set by the value of the system ODR.
An ODR of 100 Hz and a TRANSIENT_COUNT value of 15 would result in a debounce response time of 150 ms.
Table 39. TRANSIENT_SRC Description
EA
Event Active Flag. Default value: 0
0: No event flag asserted; 1: one or more event flag has been asserted.
ZTRANSE
Z transient event. Default value: 0
0: No Z event detected, 1: Z event detected
YTRANSE
Y transient event. Default value: 0
0: No Y event detected, 1: Y event detected
XTRANSE
X transient event. Default value: 0
0: No X event detected, 1: X event detected
0x2D TRANSIENT_THS Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
Table 40. TRANSIENT_THS Description
DBCNTM
Debounce counter mode selection. Default value: 0 0: increments or decrements debounce; 1: increments or clears counter
THS[6:0]
Transient Threshold: default value: 000_0000
0x2E TRANSIENT_COUNT Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Table 41. TRANSIENT_COUNT Description
D[7-0]
Count value. Default value: 0000_0000
Table 42. TRANSIENT_COUNT relationship with the ODR
Output Data Rate (Hz)
Step
Duration Range
400
2.5 ms
2.5 ms – 0.637s
200
5 ms
5 ms – 1.275s
100
10 ms
10 ms – 2.55s
50
20 ms
20 ms – 5.1s
12.5
80 ms
80 ms – 20.4s
1.56
640 ms
640 ms – 163s



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