Sensors

Freescale Semiconductor

5

MMA8450Q

0x30: PULSE_SRC Pulse Source Register ................................................................................................................. 36

0x30 PULSE_SRC Register (Read Only) ............................................................................................................ 36

Table 44. TPULSE_SRC Description ........................................................................................................................ 36

0x31 - 0x33: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers .................................................................. 37

0x31 PULSE_THSX Register (Read/Write) ......................................................................................................... 37

Table 45. PULSE_THSX Description ........................................................................................................................ 37

0x32 PULSE_THSY Register (Read/Write) ......................................................................................................... 37

Table 46. PULSE_THSY Description ........................................................................................................................ 37

0x33 PULSE_THSZ Register (Read/Write) ......................................................................................................... 37

Table 47. PULSE_THSZ Description ........................................................................................................................ 37

0x34: PULSE_TMLT Pulse Time Window 1 Register .................................................................................................. 37

0x34 PULSE_TMLT Register (Read/Write) ......................................................................................................... 37

Table 48. Time Step for PULSE Time Limit at ODR and Power Mode ..................................................................... 37

0x35: PULSE_LTCY Pulse Latency Timer Register .................................................................................................... 38

0x35 PULSE_LTCY Register (Read/Write) ......................................................................................................... 38

Table 49. Time Step for PULSE Latency at ODR and Power Mode ......................................................................... 38

0x36: PULSE_WIND Second Pulse Time Window Register ........................................................................................ 38

0x36 PULSE_WIND Register (Read/Write) ......................................................................................................... 38

Table 50. Time Step for PULSE Detection Window at ODR and Power Mode ......................................................... 38

6.7

Auto-Sleep Registers ................................................................................................................................................ 38

0x37: ASLP_COUNT Auto-Sleep Inactivity Timer Register ......................................................................................... 38

0x37 ASLP_COUNT Register (Read/Write) ........................................................................................................ 38

Table 51. ASLP_COUNT Description ....................................................................................................................... 38

Table 52. ASLP_COUNT Relationship with ODR ..................................................................................................... 39

0x38: CTRL_REG1 System Control 1 Register ........................................................................................................... 39

0x38 CTRL_REG1 Register (Read/Write) ........................................................................................................... 39

Table 53. CTRL_REG1 Description .......................................................................................................................... 39

Table 54. Sleep Mode Poll Rate Description ............................................................................................................. 39

Table 55. System Output Data Rate Selection ..........................................................................................................39

Table 56. Full Scale Selection ................................................................................................................................... 40

0x39: CTRL_REG2 System Control 2 Register ........................................................................................................... 40

0x39 CTRL_REG2 Register (Read/Write) ........................................................................................................... 40

Table 57. CTRL_REG2 Description .......................................................................................................................... 40

0x3A: CTRL_REG3 Interrupt Control Register ............................................................................................................ 40

0x3A CTRL_REG3 Register (Read/Write) ..........................................................................................................40

Table 58. CTRL_REG3 Description .......................................................................................................................... 41

0x3C: CTRL_REG5 Register (Read/Write) .................................................................................................................. 41

0x3C CTRL_REG5 Register (Read/Write) ..........................................................................................................41

Table 59. interrupt Enable Register Description ........................................................................................................ 41

0x3C: CTRL_REG5 Interrupt Configuration Register .................................................................................................. 42

0x3C CTRL_REG5 Register (Read/Write) ..........................................................................................................42

Table 60. Interrupt Configuration Register Description ............................................................................................. 42

6.8

User Offset Correction Registers .............................................................................................................................. 42

0x3D: OFF_X Offset Correction X Register ................................................................................................................. 42

0x3D OFF_X Register (Read/Write) .................................................................................................................... 42

Table 61. OFF_X Description .................................................................................................................................... 42

0x3E: OFF_Y Offset Correction Y Register ................................................................................................................. 42

0x3E OFF_Y Register (Read/Write) .................................................................................................................... 42

Table 62. OFF_Y Description .................................................................................................................................... 42

0x3F: OFF_Z Offset Correction Z Register .................................................................................................................. 42

0x3F OFF_Z Register (Read/Write) .................................................................................................................... 42

Table 63. OFF_Z Description .................................................................................................................................... 42

Appendix A ................................................................................................................................................................................ 43

Table 64. MMA8450Q Register Map ......................................................................................................................... 43

Table 65. Accelerometer Output Data ....................................................................................................................... 45

Appendix B ................................................................................................................................................................................ 46

Figure 13. Distribution of Pre Board Mounted Devices Tested in Sockets (1 count = 3.9 mg) ................................. 46

Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg) ............................................................. 47

Figure 15. 8g Z-axis TCS .......................................................................................................................................... 50

Figure 16. 8g X-axis TCO (mg/°C) ............................................................................................................................ 51

Figure 17. 8g Y-axis TCO (mg/°C) ............................................................................................................................ 52

Figure 18. 8g Z-axis TCO (mg/°C) ............................................................................................................................ 53

Package Dimensions ............................................................................................................................................................... 54