MMA8450QT datasheet(10/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

2.3

I2C Interface Characteristic

Table 4. I2C Slave Timing Values(1)

1. All values referred to VIH (min) and VIL (max) levels.

Parameter

Symbol

I2C Standard Mode

I2C Fast Mode

Unit

Min

Max

Min

Max

SCL Clock Frequency

fSCL

100

400

kHz

Bus Free Time between STOP and START Condition

tBUF

4.7

1.3

μs

Repeated START Hold Time

tHD;STA

40.6

μs

Repeated START Setup Time

tSU;STA

4.7

0.6

μs

STOP Condition Setup Time

tSU;STO

40.6

μs

SDA Data Hold Time(2)

2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

tHD;DAT

0(3)

3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

(4)

4. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the

clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

0(3)

(4)

μs

SDA Valid Time (5)

5. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;DAT

3.45(4)

0.9(4)

μs

SDA Valid Acknowledge Time (6)

6. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;ACK

3.45(4)

0.9(4)

μs

SDA Setup Time

tSU;DAT

250

100(7)

7. A Fast-mode I2C device can be used in a Standard-mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of

the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode

I2C specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

SCL Clock Low Time

tLOW

4.7

1.3

μs

SCL Clock High Time

tHIGH

40.6

μs

SDA and SCL Rise Time

1000

20 + 0.1Cb

(8)

8. Cb = total capacitance of one bus line in pF.

300

SDA and SCL Fall Time (3)(5)(8)(9)

9. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding

the maximum specified tf.

300

20 + 0.1Cb

(8)

300

Pulse width of spikes on SDA and SCL that must be

suppressed by input filter

tSP

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