P89LPC9151FDH datasheet(38/91 Pages) NXP

38 / 91 page

P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

38 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

7.2 Enhanced CPU

The P89LPC9151/9161/9171 uses an enhanced 80C51 CPU which runs at six times the

speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock definitions

The P89LPC9151/9161/9171 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 10) and can also be optionally divided to a slower frequency (see

Section 7.10 “CCLK modification: DIVM register”).

Remark: fosc is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when

enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is CCLK

⁄

7.3.2 CPU clock (OSCCLK)

The P89LPC9151/9161/9171 provides several user-selectable oscillator options in

generating the CPU clock. This allows optimization for a range of needs from high

precision to lowest possible cost. These options are configured when the flash is

programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, or an

external clock source.

7.4 Clock output (P89LPC9171)

The P89LPC9171 supports a user-selectable clock output function on the P0.7/CLKOUT

pin. This allows external devices to synchronize to the P89LPC9171. This output is

enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1

⁄

2 that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.5 On-chip RC oscillator option

The P89LPC9151/9161/9171 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

preprogrammed value to adjust the oscillator frequency to 7.373 MHz

± 1 % at room

temperature. End-user applications can write to the TRIM register to adjust the on-chip

RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 =

1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit

(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0

allowing highest performance access. This bit can then be set in software if CCLK is

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