P89LPC9151FDH datasheet(62/91 Pages) NXP

62 / 91 page

P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

62 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

all selected channels have been converted. The process will repeat starting with the first

selected channel. Additional conversion results will again cycle through the four result

terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the first channel is placed in

the result register, AD1DAT0. The result of the conversion of the second channel is placed

in result register, AD1DAT1. The first channel is again converted and its result stored in

AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An

interrupt is generated, if enabled, after every set of four conversions (two conversions per

channel).

8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the four input channels can be selected for conversion. After each channel

is converted, an interrupt is generated, if enabled, and the A/D waits for the next start

condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,

additional Timer 0 triggers are ignored until the conversion has completed. The Timer

triggered start mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all

ADC operating modes.

8.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has

started, additional edge triggers are ignored until the conversion has completed. The edge

triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

Each of the A/D converters has both a high and low boundary limit register. The user may

select whether an interrupt is generated when the conversion result is within (or equal to)

the high and low boundary limits or when the conversion result is outside the boundary

limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt

criteria. The boundary limit may be disabled by clearing the boundary limit interrupt

enable.

An early detection mechanism exists when the interrupt criteria has been selected to be

outside the boundary limits. In this case, after the four MSBs have been converted, these

four bits are compared with the four MSBs of the boundary high and low registers. If the

four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)

an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

P89LPC9151FDH Datasheet(PDF) 62 Page - NXP Semiconductors

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