P89LPC9151FDH datasheet(41/91 Pages) NXP

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P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

41 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

7.12 Memory organization

The various P89LPC9151/9161/9171 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• XDATA

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space

addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this

space could be implemented on-chip. Extended SFRs located in XDATA.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC9151/9161/9171 has 2 kB on-chip Code memory.

7.13 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 12.

7.14 Interrupts

The P89LPC9151/9161/9171 uses a four priority level interrupt structure. This allows

great flexibility in controlling the handling of the many interrupt sources.

The P89LPC9151/9171 supports 13 interrupt sources: external interrupts 0 and 1, timers

0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect,

watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, A/D completion.

The P89LPC9161 supports 13 interrupt sources: external interrupts 0, timers 0 and 1,

serial port TX, serial port RX, combined serial port RX/TX, brownout detect,

watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, ADC completion.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Table 12.

On-chip data memory usages

Type

Data RAM

Size (bytes)

DATA

Memory that can be addressed directly and indirectly

128

IDATA

Memory that can be addressed indirectly

256

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