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P89LPC9151FDH Datasheet(PDF) 61 Page - NXP Semiconductors |
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P89LPC9151FDH Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 91 page ![]() P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 61 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Edge triggered. 8-bit conversion time of ≥ 1.61 μs at an A/D clock of 8.0 MHz. Interrupt or polled operation. Boundary limits interrupt. DAC output to a port pin with high output impedance. Clock divider. Power-down mode. 8.3 Block diagram 8.4 ADC operating modes 8.4.1 Fixed channel, single conversion mode A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes. 8.4.2 Fixed channel, continuous conversion mode A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result register. The user may select whether an interrupt can be generated after every four conversions. Additional conversion results will again cycle through the four result register, overwriting the previous results. Continuous conversions continue until terminated by the user. 8.4.3 Auto scan, single conversion mode Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. 8.4.4 Auto scan, continuous conversion mode Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after Fig 21. ADC block diagram SAR 002aaa783 8 cclk comp DAC1 INPUT MUX |
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