P89LPC9151FDH datasheet(40/91 Pages) NXP

40 / 91 page

P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

40 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

7.9 CCLK wake-up delay

The P89LPC9151/9161/9171 has an internal wake-up timer that delays the clock until it

stabilizes depending on the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles

plus 60

μs to 100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to

300

μs. If the clock source is watchdog oscillator or external clock, the delay is

32 OSCCLK cycles.

7.10 CCLK modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.11 Low power select

The P89LPC9151/9161/9171 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the

power consumption further. On any reset, CLKLP is logic 0 allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

P89LPC9151FDH Datasheet(PDF) 40 Page - NXP Semiconductors