MC9S08DN60F1CLF datasheet(225/356 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S08SPIV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

225

pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT

waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master

SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at

the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a

slave.

Figure 12-10. SPI Clock Formats (CPHA = 1)

When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not

deﬁned until the ﬁrst SPSCK edge. The ﬁrst SPSCK edge shifts the ﬁrst bit of data from the shifter onto

the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the

master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the

third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,

and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the

master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive

high level between transfers.

Figure 12-11 shows the clock formats when CPHA = 0. At the top of the ﬁgure, the eight bit times are

shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last

SPSCK edge. The MSB ﬁrst and LSB ﬁrst lines show the order of SPI data bits depending on the setting

BIT TIME #

(REFERENCE)

MSB FIRST

LSB FIRST

SPSCK

(CPOL = 0)

SPSCK

(CPOL = 1)

SAMPLE IN

(MISO OR MOSI)

MOSI

(MASTER OUT)

MISO

(SLAVE OUT)

SS OUT

(MASTER)

SS IN

(SLAVE)

BIT 7

BIT 0

BIT 6

BIT 1

BIT 2

BIT 5

BIT 1

BIT 6

BIT 0

BIT 7

...

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