MC9S08DN60F1CLF datasheet(99/356 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

6.5.5

Port E Registers

Port E is controlled by the registers listed below.

6.5.5.1

Port E Data Register (PTED)

6.5.5.2

Port E Data Direction Register (PTEDD)

76543210

PTED7

PTED6

PTED5

PTED4

PTED3

PTED2

PTED11

Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit.

PTED0

Reset:

00000000

Figure 6-32. Port E Data Register (PTED)

Table 6-30. PTED Register Field Descriptions

Field

Description

7:0

PTED[7:0]

Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port E pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures

all port pins as high-impedance inputs with pull-ups disabled.

76543210

PTEDD7

PTEDD6

PTEDD5

PTEDD4

PTEDD3

PTEDD2

PTEDD11

PTEDD1 has no effect on the input-only PTE1 pin.

PTEDD0

Reset:

00000000

Figure 6-33. Port E Data Direction Register (PTEDD)

Table 6-31. PTEDD Register Field Descriptions

Field

Description

7:0

PTEDD[7:0]

Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for

PTED reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.

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