MC9S08DN60F1CLF datasheet(34/356 Pages) FREESCALE

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Chapter 3 Modes of Operation

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

3.6.1.2

Active BDM Enabled in Stop3 Mode

Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This

STOP instruction, the system clocks to the background debug logic remain active when the MCU enters

stop mode. Because of this, background debug communication remains possible. In addition, the voltage

regulator does not enter its low-power standby state but maintains full internal regulation.

Most background commands are not available in stop mode. The memory-access-with-status commands

do not allow memory access, but they report an error indicating that the MCU is in either stop or wait

mode. The BACKGROUND command can be used to wake the MCU from stop and enter active

background mode if the ENBDM bit is set. After entering background debug mode, all background

commands are available.

3.6.2

Stop2 Mode

Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most

of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering

stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.

Exit from stop2 is performed by asserting RESET. On 3M05C or older masksets only, exit from stop2 can

also be performed by asserting PTA7/ADP7/IRQ.

NOTE

On 3M05C or older masksets only, PTA7/ADP7/IRQ is an active low

wake-up and must be conﬁgured as an input prior to executing a STOP

instruction to avoid an immediate exit from stop2. PTA7/ADP7/IRQ can be

disabled as a wake-up if it is conﬁgured as a high driven output. For lowest

power consumption in stop2, this pin should not be left open when

conﬁgured as input (enable the internal pullup; or tie an external

pullup/down device; or set pin as output).

In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.

Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):

•

All module control and status registers are reset

•

The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD

trip point (low trip point selected due to POR)

•

The CPU takes the reset vector

In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This ﬂag is used to

direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched

until a 1 is written to PPDACK in SPMSC2.

MC9S08DN60F1CLF Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc