MC9S08DN60F1CLF datasheet(80/356 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

In general, whenever a pin is shared with both an alternate digital function and an analog function, the

analog function has priority such that if both the digital and analog functions are enabled, the analog

function controls the pin.

It is a good programming practice to write to the port data register before changing the direction of a port

pin to become an output. This ensures that the pin will not be driven momentarily with an old data value

that happened to be in the port data register.

Figure 6-1. Parallel I/O Block Diagram

6.2

Pull-up, Slew Rate, and Drive Strength

Associated with the parallel I/O ports is a set of registers located in the high page register space that operate

independently of the parallel I/O registers. These registers are used to control pull-ups, slew rate, and drive

strength for the pins.

An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up

enable register (PTxPEn). The pull-up device is disabled if the pin is conﬁgured as an output by the parallel

I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up

enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function.

Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control

reduce EMC emissions. Slew rate control has no effect on pins that are conﬁgured as inputs.

NOTE

Slew rate reset default values may differ between engineering samples and

ﬁnal production parts. Always initialize slew rate control to the desired

value to ensure correct operation.

Port Read

PTxDDn

PTxDn

Output Enable

Output Data

Input Data

Synchronizer

Data

BUSCLK

MC9S08DN60F1CLF Datasheet(PDF) 80 Page - Freescale Semiconductor, Inc