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MC9S08DN60F1CLF Datasheet(PDF) 26 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 26 Page - Freescale Semiconductor, Inc |
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26 / 356 page ![]() Chapter 2 Pins and Connections MC9S08DN60 Series Data Sheet, Rev 3 26 Freescale Semiconductor 2.2 Recommended System Connections Figure 2-4 shows pin connections that are common to MC9S08DN60 Series application systems. Figure 2-4. Basic System Connections (Shown in 64-Pin Package) NOTES: 1. External crystal circuit not required if using the internal clock option. 2. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM command. 3. RC filter on RESET pin recommended for noisy environments. 4. For 32-pin and 48-pin packages: VDDA and VSSA are double bonded to VREFH and VREFL respectively. PORT A C2 C1 X1 RF RS PTA0/PIA0/ADP0/MCLK PTA1/PIA1/ADP1/ACMP1+ PTA2/PIA2/ADP2/ACMP1- PTA3/PIA3/ADP3/ACMP1O PTA4/PIA4/ADP4 PTA5/PIA5/ADP5 PTA6/PIA6/ADP6 PTA7/PIA7/ADP7/IRQ PORT B PTB0/PIB0/ADP8 PTB1/PIB1/ADP9 PORT C PORT D PTD2/PID2/TPM1CH0 PTD3/PID3/TPM1CH1 PTD4/PID4/TPM1CH2 PTD5/PID5/TPM1CH3 PORT E PORT G PTG2 PTG3 PTG4 PTG5 PORT F IRQ MC9S08DN60 PTG0/EXTAL PTG1/XTAL PTF0 PTF1 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTF4/ACMP2+ PTF5/ACMP2– PTF6/ACMP2O PTF7 PTE0/TxD1 PTE1/RxD1 PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTE6 PTE7 PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 PTB2/PIB2/ADP10 PTB3/PIB3/ADP11 PTB4/PIB4/ADP12 PTB5/PIB5/ADP13 PTB6/PIB6/ADP14 PTB7/PIB7/ADP15 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTD6/PID6/TPM1CH4 PTD7/PID7/TPM1CH5 CBY 0.1 μF VREFH VREFL VSSA VDDA VDD VSS CBY 0.1 μF CBLK 10 μF + 5 V + SYSTEM POWER BKGD/MS RESET OPTIONAL MANUAL RESET VDD BACKGROUND HEADER 0.1 μF VDD 4.7 k Ω–10 kΩ |
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