MC9S08DN60F1CLF datasheet(302/356 Pages) FREESCALE

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Chapter 16 Development Support

MC9S08DN60 Series Data Sheet, Rev 3

302

Freescale Semiconductor

16.4.1.1

BDC Status and Control Register (BDCSCR)

This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)

but is not accessible to user programs because it is not located in the normal memory map of the MCU.

76543210

ENBDM

BDMACT

BKPTEN

FTS

CLKSW

WSF

DVF

Normal

Reset

00000000

Reset in

Active BDM:

11001000

= Unimplemented or Reserved

Figure 16-5. BDC Status and Control Register (BDCSCR)

Table 16-2. BDCSCR Register Field Descriptions

Field

Description

ENBDM

Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly

after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal

reset clears it.

0 BDM cannot be made active (non-intrusive commands still allowed)

1 BDM can be made active to allow active background mode commands

BDMACT

Background Mode Active Status — This is a read-only status bit.

0 BDM not active (user application program running)

1 BDM active and waiting for serial commands

BKPTEN

BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)

control bit and BDCBKPT match register are ignored.

0 BDC breakpoint disabled

1 BDC breakpoint enabled

FTS

Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the

BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register

causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,

the CPU enters active background mode rather than executing the tagged opcode.

0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that

instruction

1 Breakpoint match forces active background mode at next instruction boundary (address need not be an

opcode)

CLKSW

Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC

clock source.

0 Alternate BDC clock source

1 MCU bus clock

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