MC9S08DN60F1CLF datasheet(176/356 Pages) FREESCALE

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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

MC9S08DN60 Series Data Sheet, Rev 3

176

Freescale Semiconductor

If the MODE bits are changed, any data in ADCRH becomes invalid.

10.3.4

Data Result Low Register (ADCRL)

ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an

8-bit conversion. This register is updated each time a conversion completes except when automatic

compare is enabled and the compare condition is not met. When a compare event does occur, the value is

the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit

mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result

registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the

intermediate conversion results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE

bits are changed, any data in ADCRL becomes invalid.

10.3.5

Compare Value High Register (ADCCVH)

In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the

compare function is enabled, these bits are compared to the upper four bits of the result following a

conversion in 12-bit mode.

7654

210

ADR11

ADR10

ADR9

ADR8

Reset:

Figure 10-5. Data Result High Register (ADCRH)

7654

210

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

ADR0

Reset:

Figure 10-6. Data Result Low Register (ADCRL)

7654

210

000

ADCV11

ADCV10

ADCV9

ADCV8

Reset:

Figure 10-7. Compare Value High Register (ADCCVH)

MC9S08DN60F1CLF Datasheet(PDF) 176 Page - Freescale Semiconductor, Inc

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