68HC05CT4 datasheet(60/142 Pages) FREESCALE

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16-Bit Timer

General Release Specification

MC68HC05CT4 — Rev. 2.0

16-Bit Timer

8.3 Counter Register

The key element in the programmable timer is a 16-bit, free-running

counter or counter register, preceded by a prescaler that divides the

internal processor clock by four. The prescaler gives the timer a

resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The

counter is incremented during the low portion of the internal bus clock.

Software can read the counter at any time without affecting its value.

The double-byte, free-running counter can be read from either of two

locations, $18–$19 (counter register) or $1A–$1B (counter alternate

receives the count value at the time of the read. If a read of the free-

running counter or counter alternate register first addresses the most

significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a

buffer. This buffer value remains fixed after the first MSB read, even if

the user reads the MSB several times. This buffer is accessed when

reading the free-running counter or counter alternate register LSB ($19

or $1B) and, thus, completes a read sequence of the total counter value.

In reading either the free-running counter or counter alternate register, if

the MSB is read, the LSB also must be read to complete the sequence.

The counter alternate register differs from the counter register in one

respect: a read of the counter register MSB can clear the timer overflow

flag (TOF). The counter alternate register can be read at any time

without the possibility of missing timer overflow interrupts due to clearing

of the TOF.

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68HC05CT4 Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc