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68HC05CT4 Datasheet(PDF) 70 Page - Freescale Semiconductor, Inc |
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68HC05CT4 Datasheet(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 142 page  Synchronous Serial Interface (SSI) General Release Specification MC68HC05CT4 — Rev. 2.0 Synchronous Serial Interface (SSI) Transmission in master mode is initiated by a write to the SSI data register (SDR). A transfer cannot be initiated in slave mode; the external master initiates the transfer. The programmer must choose between master or slave mode before the SSI is enabled. The programmer must ensure that only one master exists in the system at any one time. All devices in the system must operate with the same clock polarity and data rates. Slaves should always be disabled before the master is disabled. Figure 9-1. SSI Block Diagram INTERRUPT CIRCUIT TO INTERRUPT LOGIC SSI STATUS REG. SSI CONTROL REG. SSI DATA REG. HFF SDIO SCK CLOCK GENERATOR SE LSBF CONTROL LOGIC 000000 DATA BUS CONTROLS/ADDRESS BUS MCU INTERNAL BUS MSTR & Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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