TLK6002 datasheet(5/96 Pages) TI

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REFCLK_0_P/N

REFCLK_1_P/N

REFCLK_A_SEL

REFCLK_B_SEL

S/W

0.1

S/W

0.0

RXBCLK_A

TXBCLK_A

RXDA[9:0]

TXDA[9:0]

Channel A

SERDES

REFCLKP/N

RXBCLK_B

TXBCLK_B

RXDB[9:0]

TXDB[9:0]

ChannelB

SERDES

REFCLKP/N

CLK_OUT_SEL

1/N

0.5:4

RXAP

RXAN

TXAP

TXAN

RXBP

RXBN

TXBP

TXBN

CLK_OUT_P/N

= PrimaryDevicePin

S/W

x.x:x

Legend:

= SoftwareProgrammable / Register Address.Bit

RXBCLK_*, TXBCLK_* frequencyisSerialBitRateDividedby 10

RXBCLK_* isreferredtoastherecoveredbyteclock, andisalways

synchronouswiththeincomingserialdatarate (whenvalid).

S/W

0.6

ARSChannel A

ARSChannelB

ARS

Control /

Divider

IncomingSerialBitRate *(1/2/4/8 Full/Half/Quarter/Eighth)/ 4

Note: AlsoequalinfrequencytoMPY*REFCLK/2

TDA_[19:0]

TDB_[19:0]

A S/W

3.10

BS/W

3.10

TX A FIFO

TXBFIFO

TXDB_INT[9:0]

TXBCLK_B

TXDA_INT[9:0]

TXBCLK_A

TXCLK_B

TXCLK_A

TX A Datapath

CH A TX

Datapath

TXDA[9:0]

TXBCLK_A

TX A Datapath

Channel A

TXSERDES

TX A Datapath

CHB TX

Datapath

TXDB[9:0]

TXBCLK_B

TX A Datapath

ChannelB

TXSERDES

= PrimaryDevicePin

S/W

x.x:x

Legend:

= SoftwareProgrammable / Register Address.Bit

RXBCLK_*, TXBCLK_* frequencyisSerialBitRateDividedby 10

TLK6002

www.ti.com

SLLSE34 – MAY 2010

Figure 1-3. TLK6002 Reference Clock/Output Clock Architecture

Figure 1-4. TLK6002 Transmit Clock Architecture

Introduction

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