TLK6002 datasheet(7/96 Pages) TI

7 / 96 page

TLK6002

www.ti.com

SLLSE34 – MAY 2010

Description

2.1

Pin Descriptions

Table 2-1. Pin Description – Signal Pins

Terminal

Direction

Type

Description

Signal

BGA

Supply

Channel A:

Serial Transmit Channel A Output. TXAP and TXAN comprise the transmit direction Channel A differential serial

high speed output signal.

Output

During device reset (RESET_N asserted low) these pins are driven differential zero.

TXAP

CML

TXAN

These CML outputs must be AC coupled.

AVDD

During pin based power down (PD_TRXA_N asserted low), these pins are floating.During register based power

down (1.15 asserted high), these pins are floating.

RXAP

Input CML

Serial Receive Channel A Input. RXAP and RXAN comprise the receive direction Channel A differential high

RXAN

AVDD

speed serial input signal. These signals must be AC coupled.

Transmit Input Channel A Clock. TXCLK_A is used to sample Channel A input parallel data (TDA_[19:0]).

This input must be synchronous (0 ppm) to the SERDES reference clock.

Input HSTL

TXCLK_A

1.5V/1.8V

In SDR mode, this signal is equal in frequency to serial bit rate / 20.

VDDQA

In DDR mode, this signal is equal in frequency to serial bit rate / 40.

If unused in the application, this input must be grounded.

Parallel Input Channel A Transmit Data Bus.

These data signals are synchronous to and sampled by TXCLK_A.

Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols

per TXCLK_A cycle, and DDR has four valid symbols per TXCLK_A cycle.

When input data is in 8b/10b encoded format (a.k.a. 20-bit data mode), TDA_[19:10] and TDA_[9:0] each carry a

symbol.

When input data is encoded internal to TLK6002 (8b/10b encoder enabled, a.k.a. 16-bit data mode), two symbols

Input

are input at a time, defined as follows:

HSTL

TDA_[19:0 ]

1.5V/1.8V

One Symbol – TDA_[8] contains the control bit (k-character indication) of data byte TDA_[7:0], and TDA_[9] is

VDDQA

unused and should be grounded.

Other Symbol – TDA_[18] contains the control bit (k-character indication) of data byte TDA_[17:10], and TDA_[19] is

unused and should be grounded.

Unused parallel input pins must be grounded.

See the following figures for more detail:

Figure 2-1 20-bit SDR Parallel Interface Mode.

Figure 2-2 16-bit SDR Parallel Interface Mode.

Figure 2-3 20-bit DDR Parallel Interface Mode

Parallel Channel A Receive Data Bus.

These output receive data signals are synchronous to RXCLK_A.

Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols

per RXCLK_A cycle, and DDR has four valid symbols per RXCLK_A cycle.

When output data is in 8b/10b encoded format (a.k.a. 20-bit data mode), RDA_[19:10] and RDA_[9:0] each carry a

symbol.

When output data is decoded internal to TLK6002 (8b/10b decoder enabled, a.k.a. 16-bit data mode), two symbols

are output at a time, defined as follows:

Output

One Symbol – RDA_[8] contains the control bit (k-character indication) of data byte RDA_[7:0], and RDA_[9]

HSTL

indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that

RDA_[19:0]

1.5V/1.8V

particular symbol

VDDQA

Other Symbol – RDA_[18] contains the control bit (k-character indication) of data byte RDA_[17:10], and RDA_[19]

indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that

particular symbol.

During device reset (RESET_N asserted low) these pins are driven low.During pin based power down

(PD_TRXA_N asserted low), these pins are floating.During register based power down (1.15 asserted high), these

pins are floating.

See the following figures for more detail:

Figure 2-1 20-bit SDR Parallel Interface Mode.

Figure 2-2 16-bit SDR Parallel Interface Mode.

Figure 2-3 20-bit DDR Parallel Interface Mode.

Description

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